The present invention relates to an improved semiconductor-chip testing apparatus, semiconductor testing circuit chip, and probe card, each of which is used for testing semiconductor integrated circuits.
In recent years, a time period for testing DRAMs has significantly increased due to the increasing capacities thereof or for other reasons. Test-cost reducing technology is a key to the fabrication of DRAMs with a density on the order of 1G bits. DRAMs can be subdivided into the following two types in terms of their applications:
(1) FOM (Function Oriented Memory)
Memories under this category includes ASMs (Application Specified Memories), which are memories developed exclusively for a specific use. A video memory having an image processing function is representative of these memories.
(2) COM (Cost Oriented Memory)
Memories under this category includes versatile memories. There is a possibility that quasi-versatile memories, such as synchronous memories, may fall into this category in future. Since these memories are mass-produced to reduce their costs and prices, the problem of cost reduction is critical to the very future existence of the COMs. Among the costs of producing these memories, a memory-testing period, that is, a time period required for selecting non-defective products out of all the memory chips that were obtained through the semiconductor fabrication processes has considerably increased.
FIG. 19 is a view schematically showing the structure of a conventional test system. According to the test system, one memory tester is used for testing a plurality of semiconductor integrated-circuit chips (DUT: Device Under Test). The conventional test system will be described with reference to the drawing, which shows the main body 351 of the memory tester including a fail bit memory and a controller, a VKT (Video Keyboard Terminal) 352, and a tester head 353 for applying a test voltage to semiconductor integrated circuits under test DUT0 to DUT3. With the conventional test system, however, the ratio of test cost to the total process cost of memory chips will be increasing as shown in FIG. 20. According to the trend graph of FIG. 20, the ratio of test cost will be exceeding 404 in the generation of 1G-bit memory chips, which will make the memory-chip fabrication industry no more profitable. The test-cost trend was determined based on the following data.
As an index for determining the process-cost trend, there were used expected amounts of plant and equipment investment, which are from the data presented by Komiya of Mitsubishi Electric Corporation at the 1991 Joint Meeting of the Institutes of Electricity and Information Engineers. The expected amounts of plant and equipment investment in respective generations are shown as relative values by setting the amount in the 1M-bit generation to 1, which are: 1M(1.0), 4M(2.7), 16M(6.7), 64M(20), 256M(33), and 16(67). The tester price in each generation was determined on the supposition that it would double at the latest period of each generation. That is, if the tester price in the 1M-bit generation is set to 1, the relative tester prices in respective generations are: M(1), 4M(2), 16M(4), 64M(8), 256M(16), and 16(32). The test periods in the respective generations were estimated as relative values by setting the test period in the 1M-bit generation to 1, as shown in Table 1, which are: M(1), 4M(3.2), 16M(9.6), 64M(32), 256M(90), and 1G(270).
As the trend of the number of chips which can be tested simultaneously, three cases are assumed as shown in Table 2. The production scale and the number of production items are major factors in determining which case is valid for a specific company.
TABLE 1 ______________________________________ 1 M 4 M 16 M 64 M 256 M 1 G ______________________________________ CYCLE TIME 100 80 60 50 40 30 (ns) CAPACITY 1 4 16 64 256 1024 TEST PERIOD 1 3.2 9.6 32 90 270 RATIO ______________________________________
TABLE 2 ______________________________________ 1 M 4 M 16 M 64 M 256 M 1 G ______________________________________ CASE 1 1 1 1 1 1 1 CASE 2 1 1 2 2 4 4 CASE 3 1 1 4 4 16 16 ______________________________________
In CASE1, the number of chips simultaneously tested will not change throughout the generations.
In CASE2, the number of chips simultaneously tested will double every two generations.
In CASE3, the number of chips simultaneously tested will quadruple every two generations.
In each case, the number of chips simultaneously tested is standardized by setting the number in the 1M-bit generation to 1.
FIG. 20 shows the expected trend of the ratio of test cost to the total cost, which was obtained based on the foregoing data by using the following equation: EQU Test Cost=(Tester Price).times.(Test Period)/(Number of Chips Simultaneously Tested)
The two major factors which prevent the reduction in test cost with the conventional test system are: (1) a considerable rise in tester price; and (2) a great difficulty in testing an extremely large number of chips simultaneously.
However, since semiconductor testing apparatus of the foregoing conventional structure have various analyzing functions for correspondingly testing various items of semiconductor integrated-circuit chips, it is difficult to provide them at a reduced price. In order to greatly increase the number of semiconductor integrated-circuit chips which can be simultaneously tested, it is also required to increase the number of expensive tester heads. Moreover, in the case where a failure is detected in a semiconductor integrated circuit, the capacity of a failure address storage memory for storing the failure address should also be increased to a great extent, resulting in the high prices of the semiconductor testing apparatus. Therefore, it was difficult to provide a semiconductor testing apparatus which can test a large number of chips simultaneously.